Nonvolatile memories are used in server devices, personal computers, mobile devices, and storage devices represented by solid state drives (SSDs) and the like. As the nonvolatile memories, there are flash memories, ferroelectric random access memories (FeRAMs), and magnetoresistive random access memories (MRAMs). For example, flash memories are implemented in SSDs, and data is electrically stored in and read from the flash memories. The SSDs with the flash memories consume low power and have high shock resistance, while the sizes, thicknesses, and weights of devices including the SSDs may be small. Thus, in recent years, SSDs have been used as storage systems in a large number of devices.
As an example of a nonvolatile memory element, an example of the configuration of each of memory elements of a flash memory is illustrated in FIG. 7A. A source 702 and a drain 703 are formed on a substrate 701, and a floating gate 705 is formed above the substrate 701, the source 702, and the drain 703 with an insulating layer 704 interposed between the floating gate 705 and the substrate 701, the source 702, and the drain 703. In addition, a control gate 706 is formed above the floating gate 705 with the insulating layer 704 interposed between the control gate 706 and the floating gate 705. Each of the memory elements of the flash memory is constituted by a transistor with the floating gate, controls a source voltage Vs, a drain voltage Vd, and a gate voltage Vg, injects and extracts electrons into and from the floating gate 705, and controls a threshold voltage of the transistor, thereby achieving data storage.
An example of distributions of threshold voltages Vth of the memory elements of the flash memory is illustrated in FIG. 7B. In FIG. 7B, the abscissa indicates a threshold voltage, and the ordinate indicates the number of memory elements. In each memory element of the flash memory, every time data is written and deleted, an insulating layer 704 is damaged and a variation in a threshold voltage Vth increases. As indicated by solid lines 710A and 711A, in a state in which the number of times of data writing is small and insulating layers 704 are hardly damaged, variations in the threshold voltages Vth are small.
After that, when data writing and data deletion are repeatedly executed and the damage of the insulating layers 704 progresses, the variations in the threshold voltages Vth increase as indicated by broken lines 710B and 711B. Then, when the threshold voltages Vth for different data items overlap each other as indicated by 712, the data items may not be appropriately determined and may become defective. Since the memory elements of the flash memory are degraded for each time of data writing, the life of the rewritable flash memory is shorter than those of magnetic disks. Thus, in order to average the numbers of times of writing in memory elements included in an SSD, a controller included in the SSD executes control that is referred to as wear leveling.
There have been an increasing number of cases where Multiple Level Cell (MLC), in which data of 3 or more values or multiple bits is stored in each memory element, is applied from the perspective of a cost advantage that leads to a larger storage capacity for the same number of elements is obtained in MLC, compared with Single Level Cell (SLC) in which data of 2 values (or 1 bit) is stored in each memory element. Hereinafter, in the present specification, a scheme in which data of 2 values (or 1 bit) is stored in each memory element is referred to as SLC scheme, a scheme in which data of 4 values (or 2 bits) is stored in each memory element is referred to as MLC scheme, and a scheme in which data of 8 values (or 3 bits) is stored in each memory element is referred to as Triple Level Cell (TLC) scheme. For example, when the TLC scheme is applied, a capacity is increased four times (in terms of the amount of information), compared with the SLC scheme for the same number of elements.
When memory elements are miniaturized and the number of bits of data to be stored in each memory element is increased, an acceptable number of times of writing in each memory element is reduced. For example, an acceptable number of times of rewriting in each memory element in a single certain manufacturing process is the largest in the SLC scheme, and is the second largest in the MLC scheme, and is the smallest in the TLC scheme. In addition, the speed of writing data in each memory element in the TLC scheme is lower than that in the SLC, since a threshold voltage is finely controlled in the TLC scheme. As described above, the SLC is more superior in terms of the reliability and the writing speed than the TLC, while the TLC is more superior in terms of the cost advantage than the SLC. Thus, in recent years, the TLC scheme has been used in many cases. As methods of improving the reliability and the writing speed, the aforementioned process of averaging the numbers of times of writing, garbage collection, a parallel writing method, and the like are used. In addition, a technique for writing data in a binary value region within a memory from an external, transferring the data from the binary value region to a multivalued region within the memory after the writing, and improving the writing speed for the external has been proposed.
A certain SSD, which has a main storage region 801 and a redundant region 802 as illustrated in FIG. 8 and executes control to average the numbers of times of writing in memory elements, executes control to logically switch a memory element of the main storage region 801 with a memory element of the redundant region 802 before the end of the life of the memory element of the main storage region 801. A storage capacity of each of blocks BLK1 to BLKn of the main storage region 801 is equal to a storage capacity of each of redundant blocks RBLK1 to RBLKn of the redundant region 802. The aforementioned switching control is executed on a block basis. For example, if the number of times of writing in a memory element within the block BLK2 of the main storage region 801 exceeds a predetermined number or if the number of errors increases, control is executed to use one redundant block (redundant block RBLK1 in this example) of the redundant region 802 as the block BLK2. After this switching control is executed, the block BLK2 of the main storage region 801 is set to a defective block and is not accessed.
A technique has been proposed, which is to switch an operational mode of a memory chip in which data of n bits is stored in each memory element from an operational mode for storing data of n bits in each of all memory elements to an operational mode for storing data of m (m<n) bits in each of the memory elements if the number of blocks set to defective blocks after the initial use exceeds a predetermined threshold. However, when the operational mode is switched, the actual storage capacity of the memory chip is reduced to m/n of the original capacity.
As described above, if the main storage region and the other redundant region exist and a certain block of the main storage region has become defective, the control is executed to switch the defective block with a redundant block included in the redundant region and having the same size as the defective block, but the switched defective block of the main storage region is not used after the switching.
The followings are reference documents.
[Document 1] Japanese Laid-open Patent Publications No. 2011-28793 and
[Document 2] Japanese Laid-open Patent Publications No. 2008-123330.